Xilinx Vivado Essentials for the Logic Designer

Getting started with Vivado and the SDK

Xilinx Vivado can be overwhelming for a logic designer who is creating their first design for a contemporary Xilinx device.   This course describes the various design flows, including hdl only flow, block flow and a hybrid of block and hdl.  Each flow includes a simulation options, and adding the Integrated Logic Analyzer to a design.  We introduce the Vitis SDK to allow the logic designer to create simple test programs, and describe the AXI4-Lite bus which is the most common interface between processor and logic.

What you’ll learn

  • Getting started designing FPGAs with Xilinx Vivado Design Tools.

Course Content

  • Introduction –> 1 lecture • 3min.
  • Vivado HDL Design with VHDL or Verilog –> 1 lecture • 37min.
  • Vivado Block Diagram –> 1 lecture • 18min.
  • Vivado Hybrid Block Diagram / HDL Design –> 1 lecture • 26min.
  • Vivado Integrated Logic Analyzer –> 1 lecture • 8min.
  • Vivado SDK –> 1 lecture • 15min.
  • Processor / HDL Interface with AXI Bus and GPIOs –> 1 lecture • 43min.
  • Processor Interrupts from HDL –> 1 lecture • 5min.

Xilinx Vivado Essentials for the Logic Designer

Requirements

  • Working knowledge of either VHDL or Verilog.

Xilinx Vivado can be overwhelming for a logic designer who is creating their first design for a contemporary Xilinx device.   This course describes the various design flows, including hdl only flow, block flow and a hybrid of block and hdl.  Each flow includes a simulation options, and adding the Integrated Logic Analyzer to a design.  We introduce the Vitis SDK to allow the logic designer to create simple test programs, and describe the AXI4-Lite bus which is the most common interface between processor and logic.