Advanced VHDL for Verification

Generics, Alias, Records, Mutli-dimensional arrays, TestIO, Signal Hierarchy, and Bus Functional Models

The advanced VHDL course includes advanced RTL features as well as verification behavioral capabilities :

What you’ll learn

  • Advanced VHDL for verification, including TextIO, configurations, generics, records, BFM, multi-dimensional arrays, and access types..

Course Content

  • Configurations / Memories / FIFOs –> 4 lectures • 1hr 34min.
  • Signal Hierarchy , File I/O , and Psuedocode –> 3 lectures • 1hr 10min.
  • Bus Functional Models , Generate and Alias –> 3 lectures • 1hr 2min.

Advanced VHDL for Verification

Requirements

  • Experience in VHDL RTL design. Introduction to VHDL course completion recommended..

The advanced VHDL course includes advanced RTL features as well as verification behavioral capabilities :

– VHDL Configurations

– VHDL Arrays

– Modeling memories in VHDL, creating inferred memories in RTL

– Modeling and inferring FIFOs in VHDL

– VHDL Signal Hierarchy

– VHDL Generics , Records, and Alias

– VHDL File I/O , and TextIO

– Creating pseudo-code for simulations

– Developing VHDL Bus Functional Models

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