Building Custom AXI Interface Peripherals for ZYNQ Devices

All about AXI Slave Lite and AXI Stream Interface

As system complexities are growing day by day, the Zynq device alone is incapable of providing the same performance and the Pure RTL module or Programmable logic (PL) needs to be integrated along with the Zynq. As Zynq works with Advanced Extensible Peripheral (AXI), it becomes mandatory for FPGA engineers to gain a fundamental understanding of adding AXI Interface to the Verilog RTL. The AXI4 offers different variants to fit diverse application needs. Understanding of the simpler variants such as AXI Lite and AXI Stream Interface lays a foundation for building an understanding of the complex AXI4 variant such as AXI Full.

What you’ll learn

  • Building custom AXI Slave Lite Interface.
  • Handling Interrupts with Custom AXI Slave Lite Interface.
  • Creating Custom AXI Stream Interface with Vivado Template.
  • Building Custom AXI Stream Interface with Verilog RTL.
  • Writing Drivers for Custom AXI Interface.
  • Interfacing of Custom AXI Interface with Zynq devices.

Course Content

  • Section 0 : Course Framework –> 2 lectures • 8min.
  • Building AXI Slave Lite Interface : Using Vivado Template without I/O ports –> 7 lectures • 35min.
  • Building AXI Slave Lite Interface : Using Vivado Template with I/O ports –> 7 lectures • 29min.
  • Understanding AXI4-Lite Signals –> 7 lectures • 45min.
  • Adding AXI Lite Interface for existing Verilog Code –> 6 lectures • 44min.
  • Adding Interrupts to Slave Lite Interfaces –> 5 lectures • 40min.
  • Adding Interrupts with Vivado Template –> 9 lectures • 1hr 11min.
  • Adding Master Interface –> 4 lectures • 26min.
  • AXI Stream Slave Interface with Vivado Template –> 6 lectures • 39min.
  • AXI Stream Master Interface with Vivado Template –> 4 lectures • 25min.
  • AXIS Slave Interface with Verilog –> 5 lectures • 29min.
  • AXIS Master Slave Interface with Verilog –> 5 lectures • 25min.
  • Understanding Common Errors –> 2 lectures • 7min.

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Requirements

As system complexities are growing day by day, the Zynq device alone is incapable of providing the same performance and the Pure RTL module or Programmable logic (PL) needs to be integrated along with the Zynq. As Zynq works with Advanced Extensible Peripheral (AXI), it becomes mandatory for FPGA engineers to gain a fundamental understanding of adding AXI Interface to the Verilog RTL. The AXI4 offers different variants to fit diverse application needs. Understanding of the simpler variants such as AXI Lite and AXI Stream Interface lays a foundation for building an understanding of the complex AXI4 variant such as AXI Full.

This course focuses on the usage of the Vivado IP Integrator and Vivado RTL integration for building the custom AXI interface for pure Verilog modules. There are four ways to achieve the addition of the AXI interface to the Verilog RTL viz. Using Vivado IP Packager, Vivado RTL Integration, Using System Generator, Using Vivado HLS. The course discusses two methodologies viz. Vivado IP Packager and Vivado RTL Integration in details with a simple example along with the demonstration of the integration of the created IP with the Zynq device. It will also discuss the creation of some basic device drivers, showing how software can be written to access the registers on the custom peripheral.

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