Digital Design using Verilog HDL programming with practical

design & verification with examples & applications

This is a complete Verilog HDL programming course for beginners as well as higher level, as it is from scratch to the application level. This course not only discuss the concepts in Verilog HDL programming but also discuss the applications.

What you’ll learn

  • Learning Verilog HDL Programming concepts with examples.
  • Writing complete design & test bench programming for modules like Memory controllers, FIFO controller, Random data generators, Error detection correction using Hamming code and file representation input & output etc..
  • How to use task & system tasks in Test bench.
  • How to draw Finite state machine (FSM) and how to write verilog program for any FSM and Sequence detector FSM.

Course Content

  • Introduction to the course –> 2 lectures • 26min.
  • Introduction to Verilog HDL –> 1 lecture • 11min.
  • VLSI design flow ( FPGA & ASIC) –> 1 lecture • 3min.
  • Three levels of verilog design Description –> 1 lecture • 5min.
  • Verilog Language constructs & Data types –> 2 lectures • 8min.
  • Verilog Program structure –> 1 lecture • 5min.
  • Gate level modeling –> 1 lecture • 3min.
  • Data flow modeling –> 1 lecture • 7min.
  • Behavioral Modeling –> 9 lectures • 34min.
  • Switch level modeling –> 1 lecture • 4min.
  • Test bench –> 3 lectures • 19min.
  • Functions & Task and system tasks –> 4 lectures • 19min.
  • FSM –> 1 lecture • 15min.
  • Sequence detector using FSM with complete Design & TB –> 2 lectures • 11min.
  • Memory controller –> 1 lecture • 11min.
  • FIFO –> 1 lecture • 16min.
  • Hamming code complete Design & TB for error detection & correction –> 1 lecture • 24min.
  • FPGA –> 1 lecture • 17min.

Digital Design using Verilog HDL programming with practical

Requirements

  • basic in C-programming.
  • basics Digital design ( we are designing digital circuits, but no need of digital knowledge to design a complex circuits).

This is a complete Verilog HDL programming course for beginners as well as higher level, as it is from scratch to the application level. This course not only discuss the concepts in Verilog HDL programming but also discuss the applications.

This course gives clear picture on simulation and writing a test bench using task and system task and illustrated with examples. For that, it provides file based examples like writing data in to file, reading data from file and loading data in to memory. Also some general examples like counter, clock diver using counter, pulse generator and random generator.

This course used to build Finite State Machines (FSM) diagram from the requirements and realization of FSM in to hardware model, then translation of hardware model FSM into verilog code for both Mealy & Moore and demonstrated with examples.

This course also shows some projects like Memory controller, FIFO controller and Error detection & correction using Hamming code. and finally it gives basic knowledge on FPGA’s.