FPGA Design : Glitch in Counters – Analysis using Simulator

VHDL Programs for Xilinx FPGA ,it’s Synthesis & Glitch Analysis using Timing Simulation for Various Synchronous Counters

Hello Dear Student ,

What you’ll learn

  • VHDL Programming for Various types of Synchronous Counters for Xilinx FPGA , it’s Synthesis & Comparative Glitch Analysis using Timing Simulation of Xilinx ISE Tool.

Course Content

  • Introduction – IC Technology –> 1 lecture • 19min.
  • FPGA Architecture –> 1 lecture • 21min.
  • Binary Up-Down Counter Design ( 4 Bit Synchronous Counter ) –> 4 lectures • 26min.
  • Improved Binary Up-Down Counter –> 3 lectures • 14min.
  • Applying Constraints –> 2 lectures • 28min.
  • Timing Simulation – Binary Counter –> 1 lecture • 11min.
  • Glitch in Binary Counter –> 1 lecture • 8min.
  • Gray Counter Design –> 4 lectures • 27min.
  • Timing Simulation & Glitch – Gray counter –> 1 lecture • 21min.
  • FSM Perspectives – Gray Counter for Glitch Analysis –> 6 lectures • 56min.

FPGA Design : Glitch in Counters – Analysis using Simulator

Requirements

  • Basic knowledge of Digital – Sequential Logic Design Basic knowledge of any Programming Language ( Ex. C Programming ) Basic knowledge of VHDL Programming is advantageous.

Hello Dear Student ,

I welcome you , for Enrolling this Course .

In this Course , You will Learn to write  Programs in VHDL for various types of Synchronous Counters & Synthesize it , and read the RTL Schematic as well as Technology Schematic .

You will Learn , to Write a VHDL Test Bench for Counters  and run the  Behavioral Simulation .

You will Learn , analyzing the Glitch Behavior & Pattern for Various Counter Designs using Timing Simulator using Xilinx ISE Tool .

You will understand , to compare the Performances of Glitch for various Counter Designs .