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Verilog Programming Basics for Programmable Logic IC Chips

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Learn Basic Verilog Programming Case Studies with World’s most Popular Xilinx CPLD Architecture .

Hello Dear Student ,

What you’ll learn

  • Basic Verilog Programming for simple Combinational Logics using Xilinx ISE tool for Xilinx CPLD Tool.

Course Content

  • About IC Technology –> 1 lecture • 19min.
  • FPGA Architecture –> 1 lecture • 21min.
  • Digital Logic – 1st ( With Gate Level Modeling ) –> 3 lectures • 17min.
  • Digital Logic – 2nd ( With DataFlow Modeling ) –> 3 lectures • 18min.
  • Digital Logic – 3rd ( With Behavioral Modeling ) –> 3 lectures • 18min.

Verilog Programming Basics for Programmable Logic IC Chips

Requirements

  • Basic Understanding of Digital Logic Elements . Basic level knowledge of any Programming Language like C , will be advantageous ..

Hello Dear Student ,

First of all I welcome you , for Learning this Course .

There is lot of Scope for the VLSI / IC Chip ( ASICs ) Design & Programmable IC s – FPGAs . Its applications are increasing day by day .

World’s Top Leading companies Like Intel , Apple , Xilinx , ST Microelectronics , Samsung , Sony , Philips , Microchip , ARM , AMD , nvidia ,HP , IBM , Broadcom  etc . are involved in the Design , Research & Development of IC Chip Design / Programmable IC Chip Design and also , Cadence , Synopsys , Mentor Graphics , Xilinx , Intel  etc. which are the companies involved in developing EDA Tools in which VHDL / Verilog / System Verilog Programming is used in their IDEs / Tools .

This Course is basically for first time Learner of Verilog HDL Programming & first time Learner of Programmable Digital Logic IC Concept .

It is a very short Duration course having approximately 30 to 40  Minutes of Video Content .

It gives a very quick learning Technique of Verilog HDL Programming as applied to CPLD – Programmable Logic IC Chip at a very Basic Level .

Instead of going through Books , at the beginning  , for Learning , it is a good approach to start directly the Programming Practice session & to understand the basic Design methodology / Basic Flow for Learning , without wasting much time . Later on , you may refer the Books on Verilog Programming .

I have explained 2 (Two ) Verilog Programming Case studies in this Course ,  based on Dataflow Modeling & Gate Level Modeling . .

I hope , you will enjoy learning , this Course .

 

Thank You

Pravinkumar P. Ambekar